Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm on FPGA

نویسنده

  • Ganapathi Hegde
چکیده

Today’s technological growth in the semiconductor industry has created unprecedented demand for electronic gadgets that are very sophisticated and user friendly. Interfaces with audio/video capabilities have further enhanced the demand for the products in the market. Video data needs to be compressed before storage and transmission; complex algorithms are required to eliminate the redundancy, extracting the redundant information and compression video sequences requires high speed power efficient architectures. In this paper, full search block matching algorithm (FSBMA) for motion estimation and compensation which leads to video sequence compression is realized on FPGA using systolic array architectures. The FSBMA has been designed using 2-dimensional systolic array architecture. The blocks of the architecture are processing element, shift register arrays, address generators for search area value and reference block value, enable signal generator, candidate region monitor and best match selection unit. All the blocks and the top module have been designed. In this work the two dimensional systolic array architecture with serial input is used to perform Full Search Block Matching Algorithm. The FSBMA using Systolic Array has been modeled in Verilog Hardware Description Language and simulated against its functional specifications. This is then synthesized using Xilinx synthesis tool with constraints and has been implemented on FPGA. The implemented design has been verified. The system has single clock and reset. The designed system has an image resolution of 176x144 and works at a frequency of 45.792MHz. It takes serial inputs and performs parallel processing to reduce IO pin counts. The design has been implemented on Spartan3E FPGA and the following resources have been utilized, 2095 out of 4656 slices (44%), 2816 out of 9312 slice flip-flops (30%) and 63 Input Output blocks (IOBs). The minimum period of one clock pulse is 21.838ns.

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تاریخ انتشار 2009